Third UKHEC Annual Seminar
Registration | Programme | Travel | Accommodation

Getting the Most from your Processor

9-10th December 2002, in association with 13MEW.

Daresbury Laboratory, Keckwick Lane, Daresbury, Warrington WA4 4AD, Cheshire, UK

Full programme for both days.

Note, presentation slides are included under each speaker's abstract.

Invited Speakers

Mike Ashworth (CLRC) - The UKHEC Collaboration
Jan Boerhout (NEC ESS) - High Performance through Vector-Parallel Processing
Bob Carruthers (Cray UK) - Optimisation Strategy for exploiting the Cray X1 Architecture
Gernot Hoyler (Technical Marketing Engineer, Intel, EMEA) - Getting the most out of the Intel(r) Itanium(r) Architecture
John Hague (IBM UK) - Optimisation for IBM's p690 Power4 system.
Werner Krotz-Vogel (Pallas) - Software Development Tools for Getting the Most from your Processor
Judit Gimenez (CEPBA, Barcelona) - Obtaining useful information from raw performance data
Martyn Guest (CLRC, Daresbury) - Benchmark Performance of Current Processors
Rick Kufrin (Performance Engineering and Computational Methods Group (PECM), National Computational Science Alliance (NCSA)) - Experiences with First-Generation Itanium at the National Center for Supercomputing Applications
Deborah Salmond (ECMWF) - Implementation of a global weather forecasting system on an IBM highly parallel scalar system with 960 Power4 processors.
Jennifer Scott (CLRC) - Numerical libraries, HSL and large sparse systems

The Seminar

As part of the UK High End Computing (UKHEC) collaboration, Daresbury Laboratory is organising the Third UKHEC Annual Seminar entitled Getting the Most from your Processor.

This seminar addresses topics which have not been debated for some time, but are of key importance to anyone using computer systems for scientific problem solving. The many different ways to get good performance are applicable to all computer architectures and are vendor neutral.

Speakers will address issues including: EPIC vs. RISC vs. vector architecture; hierarchical cache and memory optimisation; compiler design; performance monitoring tools; numerical libraries; multi-threading; and languages.

The annual seminars are intended to provide opportunities for scientists and engineers to keep up to date with the latest high-end computing research in the UK and beyond. The themes for this year's seminar should therefore be particularly topical.

Programme

In addition to the invited speakers above, there will be a number of presentations from the members of the UKHEC Collaboration. See the full programme for further details nearer the time.

Lunch will be provided on both days and a free wine reception for all delegates and speakers will be held on the evening of Monday 9th.

Getting Here

This event will be held at the Daresbury Laboratory, near Warrington, UK. Information on getting to the venue can be found here. A copy of an e-mail which was sent to all delegates and which contains some information on the seminar can be found here.

Accommodation

A list of hotels in the Warrington area is provided. We will update this and provide other information nearer the time.

Registration

Attendance at UKHEC events is free to UK academics. This includes coffee and lunches on both days and evening dinner on Monday 9th. Click here to register

Address

Postal address:UKHEC Annual Seminar 2002
CLRC
Daresbury Laboratory
Keckwick Lane
Daresbury
Warrington WA4 4AD, UK
Telephone:+44 (0) 1925 603207
Fax:+44 (0) 1925 603634
E-mail: Machine_Evaluation_Workshop@dl.ac.uk